1. Field of the Invention
The present invention relates to a reset method, and more particularly, to a reset method for a digital circuit and related signal generating apparatus.
2. Description of the Prior Art
A flip-flop is a widely used logic circuit device in a digital system, used for storing input data according to rising edge or falling edge of an input clock signal to achieve the objective of synchronizing the whole digital system. Taking a Delay-type Flip-Flop (DFF) as an example, there are two signals, a synchronous signal and an asynchronous signal, used to control the DFF. The synchronous signal is a clock signal, and the asynchronous signal is a preset signal or a reset signal (also referred to as a clear signal). Regardless of other input signals, the output of the flip-flop is maintained at a binary value “1” if the flip-flop is at the preset state, and the output of the flip-flop is set to another logic value “0” if the flip-flop is at the reset state.
Generally speaking, there are two problems existed when the asynchronous signal is transmitted to the flip-flop. One is the violation of asynchronous recover time and the other is the propagation delay of the asynchronous signal. For further illustration, please refer to FIG. 1. FIG. 1 is a diagram illustrating the relationship between a clock signal and a reset signal. As shown in FIG. 1, the reset signal RST is an asynchronous signal inputted to the flip-flop. If the reset signal RST has a transition from low level to high level (indicated by the dotted line in FIG. 1) at the rising edge or falling edge of the clock signal CLK, the error will occur at the output of flip-flop. To avoid the above-mentioned situation, it is necessary to maintain a timing difference between the time when the reset signal has a transition from low level to high level due to an end of the reset period and the time when the clock signal triggers the flip-flop. Another problem is the propagation delay of an asynchronous signal. This means that while a reset signal is transmitted to a plurality of flip-flops, some flip-flops are reset in a clock cycle, while others are reset in the next clock cycle because the reset signal arrives at the flip-flops at different times due to the propagation delay. As a result, error will occur at the output of flip-flops. The conventional solution is to make use of extra buffer(s) to balance the propagation delay. However, the number of required buffers increases as the number of flip-flops increases, thereby increasing the cost and the size of the circuit.